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 ESDA14V2-2BF3
Quad bidirectional TransilTM array for ESD protection
Features

2 bidirectional Transil functions ESD protection: IEC 61000-4-2 level 4 Stand off voltage: 12 V Min. Low leakage current Very small PCB area < 1.5 mm2 400 microns pitch
Flip Chip (4 bumps)
Complies with the following standards
IEC 61000-4-2 - 15 kV (air discharge) - 8 kV (contact discharge) MIL STD 883E- Method 3015-7: class 3 - 25 kV (human body model)
Figure 1.
Pin layout (bump side)
2
1 A
Applications
Where transient overvoltage protection in ESD sensitive equipment is required, such as:

B
Computers Printers Communication systems and cellular phones Video equipment Figure 2. Configuration
1 A
2
Description
The ESDA14V2-2BF3 is a monolithic array designed to protect 2 lines against ESD transients. The device is ideal for applications where both reduced line capacitance and board space saving are required. This device is particularly adapted to the protection of symmetrical signals.
B
TM: Transil is ASD a trademark of STMicroelectronics.
April 2008
Rev 3
1/9
www.st.com
Characteristics
ESDA14V2-2BF3
1
Characteristics
Table 1.
Symbol
Absolute ratings (limiting values)
Parameter MIL STD 883E - Method 3015-7 IEC 61000-4-2 air discharge IEC 61000-4-2 contact discharge Value 25 15 8 50 125 -55 to +150 260 -40 to +125 Unit
VPP PPP Tj Tstg TL Top
ESD discharge
kV W C C C C
Peak pulse power (8/20s) Junction temperature Storage temperature range Lead solder temperature (10 seconds duration) Operating temperature range
Table 2.
Symbol VBR IRM VRM VCL Rd IPP T C
Electrical characteristics (Tamb = 25 C)
Parameter Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Voltage temperature coefficient Capacitance VBR @ IR IRM @ VRM max V 18 mA 1 max. A 0.5 0.1 V 12 3 Rd
Slope: 1 / Rd IPP VCL VBR VRM V I
T
C max. 0 V bias pF 12
Order code
min. V
typ.(1) max.(2) 3.2 10-4/C 6.5
ESDA14V2-2BF3
14.2
1. Square pulse, Ipp = 3 A, tp = 2.5 s. 2.
VBR = T* (Tamb -25 C) * VBR (25 C)
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ESDA14V2-2BF3
Characteristics
Figure 3.
Relative variation of peak pulse power versus intial junction temperature
Figure 4.
Peak pulse power versus exponential pulse duration
Ppp[Tj initial] / Ppp [Tj initial=25C]
1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 150 Tj(C)
Ppp(W)
1000
Tj initial = 25C
100
tp(s) 10 1 10 100
Figure 5.
Clamping voltage versus peak pulse current (typical values, rectangular waveform)
Figure 6.
Junction capacitance versus reverse applied voltage (typical values)
10.0
IPP(A)
tp=2.5s Tj initial =25C
C(pF)
14 13 12 11 10 9 8
F=1MHz VOSC=30mVRMS Tj=25C
1.0
7 6 5 4 3
VCL(V) 0.1 0 10 20 30 40 50 60
2 1 0 0 2 4 6
VR(V) 8 10 12 14
3/9
Characteristics
ESDA14V2-2BF3
Figure 7.
Relative variation of leakage current versus junction temperature (typical values)
Figure 8.
Analog crosstalk measurement
IR [Tj ] / IR [Tj =25 C]
100
0.00
db
-30.00
10
-60.00
-90.00
T j(C) 1 25 50 75 100 125
f (Hz) -120.00 100.0k 1.0M 10.0M 100.0M 1.0G
Figure 9.
ESD response to IEC 61000-4-2 (+15 kV air discharge)
4/9
ESDA14V2-2BF3 Figure 10. ESD response to IEC 61000-4-2 (-15 kV air discharge)
Characteristics
Figure 11. Digital crosstalk measurement
5/9
Application information
ESDA14V2-2BF3
2
Application information
Figure 12. Aplac model
Ls A1 Rs Rs Ls A2
MODEL = D01
MODEL = D01
bu l k1
MODEL = D02
B1 Lg nd Rgnd Rgnd Lgnd
B2
aplacvar Ls 150 p aplacvar Rs 60 m aplacvar Lgnd 290 p aplacvar Rgnd 250 m
Model D01 BV=1 IBV=1 CJO=12.5 M=0.33 RS=0.3 VJ=0.6 TT=100
Model D02 BV=1 IBV=1 CJO=250 M=0.33 RS=80m VJ=0.6 TT=100
3
Ordering information scheme
Figure 13. Ordering information scheme
ESDA
ESD Array Breakdown Voltage 14V2 = 14.2 Volts min. Number of line 2 = 2 lines Type B = Bidirectional Package F = Flip Chip x = 3: Lead-free, pitch = 400 m, bump height = 255 m
14V2 - 2
B
F3
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ESDA14V2-2BF3
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 14. Package dimensions
400 m 40
400 m 40 185 m 10 255 m 40
605 m 55
185 m 10
770 m 30
Figure 15. Footprint
Copper pad Diameter: 220 m recommended 260 m maximum Solder mask opening: 300 m minimum
770 m 30
Figure 16. Marking
Dot xx = marking z = manufacturing location yww = datecode (y = year ww = week)
Solder stencil opening: 220 m recommended
xxz y ww
7/9
Ordering information Figure 17. Flip Chip tape and reel specifications
Dot identifying Pin A1 location 4 0.1
ESDA14V2-2BF3
O 1.5 0.1
1.75 0.1 3.5 0.1
0.87
xxz yww xxz yww xxz yww
0.71 0.05
All dimensions in mm
8 0.3
4 0.1
User direction of unreeling
0.87
Note:
More information is available in the application note: AN2348 :"400 m Flip Chip: Package description and recommendations for use" AN1751 : EMI Filters: Recommendations and measurements
5
Ordering information
Table 3. Ordering information
Marking EG Package Flip Chip Weight 0.79 mg Base qty 5000 Delivery mode Tape and reel 7"
Order code ESDA14V2-2BF3
6
Revision history
Table 4.
Date 02-Dec-2005 15-Dec-2005 29-Apr-2008
Document revision history
Revision 1 2 3 Initial release. Ordering information changed. Updated ECOPACK statement. Updated Figure 13 and Figure 17. Reformatted to current standards. Changes
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ESDA14V2-2BF3
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